The present invention relates to semiconductor devices and, more specifically, to co-integration of elastic and plastic relaxation on the same wafer.
In current or conventional semiconductor device manufacturing, some semiconductor devices are characterized in that they are manufactured to include a blanket silicon germanium (SiGe) layer that is grown everywhere on a wafer. This can occur even if that wafer includes n-doped field effect transistor (nFET) sections, in which tensile silicon (Si) is used, and p-doped field effect transistor (pFET) sections, in which compressive SiGe is used.
This situation leads to a requirement that a very high percentage or concentration of germanium (Ge) in layers of the pFET sections be grown over relaxed SiGe layers in order to generate sufficient compressive stress in the channel material. Defect formation can be an issue during the plastic relaxation of SiGe, especially if the thickness or Ge concentration is too important. In order to avoid degraded device performance and defect formation in FinFET technologies, it is possible to use the elastic relaxation of SiGe, but such elastic relaxation is not normally applicable to static random access memory (SRAM) regions where fins are typically never cut.